Sagar Phatak is a Senior Staff Application Engineer at Synopsys, bringing over 8 years of experience in designing, developing, and analyzing ASIC performance models. Previously, they served as a Senior Software Engineer at Intel Corporation, where they designed SystemC-based Ethernet subsystems and collaborated closely with design teams to resolve performance issues. Sagar also held engineering roles at Ericsson, focusing on full chip performance models, and interned as a Networking Software Architect. They earned a Master of Science in Computer Science from the University of Southern California and a Bachelor of Engineering in Computer Science from Pune Institute of Computer Technology.
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