Sai Kumar Jyothi is a Senior Analog Design Engineer at Synopsys Inc., where they contribute to cutting-edge technology in microelectronics and VLSI. Currently pursuing a Master of Technology in Microelectronics and VLSI at the Indian Institute of Technology, Hyderabad, Sai holds a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Kakatiya Institute of Technology & Science. Previously, they worked as an FPGA Design Engineer at MEDHA SERVO DRIVES PVT LTD, focusing on RTL design, simulation, and testing of FPGA designs, and have experience with various communication protocols. Additionally, Sai completed internships at GlobalFoundries and Electronics Corporation of India Limited, further enhancing their technical skills in circuit design and simulation.
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