saisrujana patha

Saisrujana Patha is a Senior Application Engineer at Synopsys Inc, where they focus on signoff static timing analysis. They previously served as a Graduate Technical Intern at Intel Corporation, contributing to standard cell and physical design processes. Saisrujana gained experience as a Physical Design Trainee at VLSIGuru Training Institute and as an Advanced Physical Design and Verification Trainee at Maven Silicon, where they honed their skills in VLSI fundamentals. Saisrujana holds a Master of Science in Electrical and Computer Engineering from Portland State University and a Bachelor of Technology in Electronics and Communication Engineering from JNTUH College of Engineering Hyderabad.