Sajith P is an experienced Design Engineer with a notable background in the semiconductors and software industries. Currently serving as a Staff Engineer in ASIC RTL Design at Synopsys, they previously held the position of SoC Logic Design Engineer at Intel Corporation from 2018 to 2024, and prior to that worked as a Software Engineer at QuEST Global. Sajith holds a Master of Technology (MTech) in VLSI and Embedded Systems and a Bachelor of Technology (B.Tech.) in Electronics and Communication Engineering, both from Model Engineering College.
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