Sanat Kumar is a Senior ASIC Digital Design Verification Engineer at Synopsys, where they have nearly two years of experience focusing on building and optimizing UVM-based verification environments for complex IPs. Prior to this role, Sanat completed a summer internship at Ansys and contributed as a mentor and member at IEEE DTU. They hold a B.Tech in Electrical Engineering from Delhi Technological University with a 9.07 CGPA, and they are currently engaged in JEE advanced preparation. Sanat is skilled in System Verilog, UVM, and various automation tools, demonstrating a strong commitment to quality and maintainability in their work.
Location
Roorkee, India
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