Sandeep Aranake

Sandeep Aranake is an accomplished Software Engineer with extensive experience in VLSI design and optimization, particularly at Synopsys from 2004 to present, where expertise encompasses logic synthesis, power analysis, and sequential optimization techniques. Previous roles include software development for CPU-based hardware acceleration at CPU Technology, Inc., FPGA synthesis at Synplicity, and contributions to logic optimization and FPGA architectures at Atmel Corporation. Sandeep's career began in 1988 at Semiconductor Complex Ltd, focusing on design rule checking systems for VLSI layouts. Academic credentials include a Master’s Degree in Computer Science from The University of Texas at Arlington and a Master of Technology in Micro Electronics from Banaras Hindu University.