Sandesh Y. is a Senior Research and Development Engineer at Synopsys Inc, where they focus on advancing semiconductor technology through innovative Design for Testability practices. Previously, they held the position of Silicon Design Engineer at AMD from 2022 to 2023. Sandesh possesses a Master of Technology in VLSI and Embedded Systems from B.M.S. College of Engineering and is currently pursuing a Bachelor of Engineering in Electrical, Electronics and Communications Engineering at Nagarjuna College of Engineering and Technology. Their expertise includes Logic BIST, DFT Compiler, and Scan Insertion, contributing significantly to the reliability and performance of advanced chip designs.
Location
Bengaluru, India
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