Sandesh Y.

Sandesh Y. is a Senior Research and Development Engineer at Synopsys Inc, where they focus on advancing semiconductor technology through innovative Design for Testability practices. They hold a Master of Technology in VLSI and Embedded Systems from B.M.S. College of Engineering and are pursuing a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Nagarjuna College of Engineering and Technology. Previously, Sandesh worked as a Silicon Design Engineer at AMD and as an R&D Engineer 2 at Synopsys Inc, contributing to the Electronic Design Automation group. Their expertise includes Logic BIST, DFT Compiler, and Scan Insertion, with a dedication to enhancing the reliability and performance of complex chip designs.