Sandhiya C

Sandhiya C is a Senior Engineer in R&D Engineering at Synopsys Inc, where they apply their expertise in ASIC Design Verification. With 3.5 years of experience in IP and subsystem verification, Sandhiya has honed skills in test bench development and protocol verification for major clients, including Google and WDC. Prior to their current role, they worked as a Verification Engineer at SmartDV Technologies. Sandhiya holds a Bachelor of Engineering in Electronics and Communication Engineering from Coimbatore Institute of Engineering and Technology, along with a strong academic background from Shri Maruthi Matriculation Higher Secondary School.