Sanjay Sivalingam

Sanjay Sivalingam is currently an ASIC Digital Design Senior Engineer at Synopsys Inc and is pursuing a Master of Engineering in Electrical and Computer Engineering at the University of Waterloo, where they maintain a 3.96 GPA. They previously completed a Bachelor of Engineering in Electronics and Communications Engineering at the College of Engineering, Guindy, with a 9.32 GPA and worked as a Project Associate at the Indian Institute of Technology, Madras. With experience in VLSI Circuits, ASIC design, and various EDA tools, Sanjay has contributed to projects that enhance performance insights for athletes and optimize agricultural data analysis. They have also interned at TSMC, focusing on RTL verification and memory circuit design.