Sarat Vegesna is a Senior Manager at Synopsys Inc, where they focus on team and account management. Previously, Sarat worked as a Verification Engineer at Toomuch Semiconductor Solutions from 2004 to 2007 and held a role as a CAE at Synopsys from 2007 to 2017, participating in VCS and AMBA VIP support activities. Sarat earned a Bachelor of Engineering in Computer Science and Engineering from Raja Rajeswari College of Engineering at the University of Madras and a Master of Engineering in Computer Systems Engineering, specializing in VLSI, from Victoria University.
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