Sharath Bhat is an ASIC Digital Designer with a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from BMS College of Engineering, which was completed in 2012. They began their career with an internship at Bharat Heavy Electricals Limited in 2011 and currently serve as a Senior RTL Design Engineer at Synopsys Inc since 2021. Skilled in hardware languages such as Verilog and proficient with various simulators and tools, Sharath brings a wealth of technical expertise to their role.
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