Sheetal SH is a Senior Engineer in ASIC digital design at Synopsys, where they have been employed since 2025. Prior to this role, Sheetal worked as an ASIC digital design engineer and contributed to core verification at VerifIQ Technologies Private Limited from 2021 to 2022, focusing on AMD64 Core verification. Sheetal earned a Master of Technology in VLSI and embedded systems from RV College of Engineering in 2022 and holds a Bachelor of Engineering in Electronics and Communications Engineering from Bapuji Institute of Engineering & Technology, completed in 2019.
Location
Karnataka, India
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