Shiqu Pu

Shiqu Pu is a Staff ASIC Design Verification Engineer at Synopsys Inc, specializing in AMS verification with expertise in AMS modeling, UVM-AMS, and cross-domain debug. With a proven record of accelerating tapeout schedules and enhancing verification efficiency through automation, Shiqu has significantly contributed to silicon success at advanced nodes. Shiqu previously interned as a Telecommunications Engineering Intern at China Mobile Group Yunnan Co. Ltd and worked as an Android Developer Intern at Tencent, where they improved project test coverage. Shiqu holds a Bachelor of Engineering from Western University and is currently pursuing a Master of Engineering at the University of Toronto.