Shreevasa Bhat is a Sr Staff Engineer specializing in layout design at Synopsys Inc, where they utilize strong and hands-on experience in both planar and cutting-edge FinFET nodes. Previously, they held positions including Staff Engineer and Analog Layout Designer at Kalatronics, providing valuable expertise as a contract engineer at Qualcomm. Shreevasa earned a Bachelor of Engineering in Electronics and Communication from PES University in 2016.
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