Siddharth Patel is a diligent and innovative design and verification engineer with over five years of experience in creating and validating Verification IP. Previously, they served as a Software Engineer II at Cadence Design Systems from 2020 to 2022 and completed an internship at DSP Group in 2019. Currently, they hold the position of Sr. R&D Engineer at Synopsys Inc. Siddharth completed their education at Nirma University in Ahmedabad, Gujarat, India, graduating in 2020.
This person is not in the org chart
This person is not in any teams
This person is not in any offices