Sudheendra Acharya

Sudheendra Acharya is a seasoned engineer currently serving as a Staff Application Engineer at Synopsys Inc since July 2018, previously holding titles such as Senior FPGA Engineer 2 and Senior FPGA Engineer, specializing in prototyping advanced SoC and IP designs on the HAPS platform. Prior to this, Sudheendra gained experience as a Graduate Teaching Assistant and Graduate Research Assistant at Oregon State University, focusing on computer networks and high-speed serial interfacing with FPGAs. Sudheendra also completed engineering internships at Diagnosys Test Systems Limited and Advanced Rail Controls Private Limited. Sudheendra holds a Master's Degree in Electrical Engineering and Computer Science from Oregon State University and a Bachelor's Degree in Electronics and Communications Engineering from Canara Engineering College.