Sudipta Mandal is a Sr. Engineer at Synopsys Inc, specializing in memory design with over three years of experience. Currently, they work in R&D engineering and have contributed to notable projects, including the development of a 22nm ULL SRAM Compiler and SF5 Pseudo Dual Port HS SRAM Compiler at M31 Technology. Previously, they held a position as an Associate Member of Technical Staff at DXCorr Design Inc, focusing on memory circuit design. Sudipta earned a Bachelor of Technology in Electronics and Telecommunications Engineering from the Indian Institute of Engineering Science and Technology (IIEST), Shibpur, in 2022.
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