Surendra Yenduri

Surendra Yenduri is an ASIC Digital Design Senior Engineer at Synopsys, currently utilizing expertise in System Verilog and UVM. With over three years of hands-on experience in verification environments, Surendra has a proven track record in developing robust verification processes and testing Ethernet features. Previously, Surendra held a position as a Senior ASIC Design Verification Engineer at Tata Elxsi and completed an advanced VLSI design and verification role at Maven Silicon. Surendra earned a Bachelor's degree in Electronics and Communications Engineering from Siddharth Institute of Engineering & Technology and a Diploma in the same field from Vasavi Polytechnic.