Suryansh Arora is a Senior Staff Engineer in ASIC Physical Design at Synopsys, specializing in transforming design concepts into high-performance chips. With hands-on experience in Physical Design at the block level, Suryansh has worked on various advanced technology nodes down to 5nm. Previous roles include Technical Leader at STMicroelectronics and innovative project work during their academic career, where Suryansh developed expertise in low-power design and ASIC design flows, including UPF integration and VCLP checks. Suryansh holds a Bachelor of Technology in Electronics and Communications Engineering and a Master of Technology in Microelectronics & VLSI Design.
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