Sushant Pathak is a Verification Engineer currently employed at Synopsys Inc. They have a diverse background, having worked as a Lead Design Engineer at Cadence Design Systems, where they specialized in PCIe IP verification. Their previous roles include Jr. Engineer VLSI at Open Silicon Research Pvt Ltd and TSE at Teleperformance. Sushant holds a Bachelor's degree in Electrical, Electronic, and Communications Engineering Technology from the International Institute of Technology and Business, as well as a post-graduation diploma in VLSI from the Centre for Development of Advanced Computing. They began their career in operations at Wipro Infotech.
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