Swetha K

Swetha K is currently an A&MS Layout Design Engineer II at Synopsys Inc, where they apply their extensive knowledge in Analog Mixed Layout Design. With over three years of experience across submicron and deep submicron technologies, Swetha has demonstrated expertise in designing and verifying analog layouts, utilizing tools such as Cadence and Assura. Prior to their role at Synopsys, Swetha worked as an Analog Layout Engineer at Altran and as a Layout Engineer at S-micron VLSI Studies in 2017.