Szu-Ying Ho is a proficient application engineer with experience at Synopsys Inc and Cadence Design Systems. At Synopsys Inc, Szu-Ying enhanced router and PG router rules while addressing client issues for prominent companies such as Intel, TSMC, and Google. Previous roles at Cadence Design Systems included product and lead product engineer, where Szu-Ying developed features for 3DIC testing, contributed to client-specific design flows, and optimized testing processes using scripting languages. Szu-Ying holds a Master of Engineering in Electrical and Electronics Engineering with a 3.9 GPA from National Taiwan University of Science and Technology.
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