Tanuj Poddar is currently a Staff R&D Engineer at Synopsys Inc, where they have been involved in developing Verification IP products for a variety of customers since 2022. Previously, Tanuj held the position of Sr. R&D Engineer at Synopsys Inc from 2022 to 2024, specializing in System Verilog language and OVM/UVM methodologies for IP verification. Tanuj's experience includes a Verification Engineer role at nSys Design Systems, where they debugged test cases and developed new test suites, as well as internships at ETA Engineering and Doordarshan Kendra, focusing on HVAC systems and television broadcasting, respectively. Tanuj holds a B.Tech degree from Maharaja Agrasen Institute of Technology, earned in 2011.
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