Tarun Degala is an experienced Design Verification Engineer with a demonstrated history in the semiconductor industry. Currently a Senior Design Verification Engineer I at Synopsys Inc, they have previously held positions at INVECAS and Soctronics. Tarun holds a Master of Technology (MTech) in VLSI from Maharaj Vijayaram Gajapathi Raj College of Engineering and a Bachelor of Technology (BTech) in Electronics and Communications Engineering from JNTU College of Engineering. They are skilled in Universal Verification Methodology (UVM), SystemVerilog, Regression Testing, and TCL.
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