Tayeb Sofiane Bouhadiba is an experienced R&D Engineer at Synopsys since October 2012, with a strong background in embedded systems and formal methods. Academic qualifications include a Ph.D. scholarship focused on Formal Methods for Embedded System Design and an M.S. in Academic Approaches to Computer Systems Design from Université de Mostaganem. Prior experience includes a postdoctoral position at Vérimag involving high-level models for low power embedded systems, a postdoc role at INRIA centered on synchronous controller synthesis, and teaching assistant roles covering various topics in software engineering and programming. Early career experience includes an engineering role at CNL - Algeria and an internship at Sonatrach related to intrusion detection systems.
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