Tej P. is a seasoned Design Engineer with extensive experience in the semiconductors industry, specializing in layout design for memory and analog systems. Tej holds a Bachelor of Technology (B.Tech.) in electronic and communication from Bundelkhand University Jhansi. Previous roles include Design Engineer at Spontey and Senior Layout Design Engineer at Altran, where they honed their skills in integrated circuits. Currently, Tej serves as a Staff Engineer at Synopsys Inc, focusing on Memory Layout Design.
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