Tejas Patil is a Senior DFT Engineer at Synopsys Inc, where they are currently engaged in advanced design-for-test activities. Previously, Tejas worked at Cientra from 2022 to 2024, focusing on logic and memory diagnostics for various SoCs and Test Chips, as well as participating in DFT-RTL verification activities in Qualcomm. Tejas has also gained experience as a DFT Engineer at Pozibility Technologies Pvt Ltd and served as a Maintenance Engineer at Bajaj Auto Ltd from 2016 to 2017. They hold a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Shivaji University, Kolhapur, and have completed a Diploma in Electronics Engineering from the Maharashtra State Board of Technical Education.
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