Tejaswi Medisetti is a Senior Analog Design Engineer at Synopsys Inc, specializing in analog circuit design and utilizing tools such as VerilogA, MATLAB, and Cadence. Previously, they worked as a Scientist at DRDO, focusing on ASIC implementations for Inertial MEMS sensors. Tejaswi also held positions as a Software Engineer at Next Education India Pvt Ltd and an AMS Design Engineer at Infineon Technologies. They earned an M.Tech in Electronic System Engineering from the Indian Institute of Science and a B.Tech in Electrical, Electronics, and Communications Engineering from JNTUH. Tejaswi has published two IEEE papers and one conference paper.
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