Tejinder Kumar

Tejinder Kumar is a System and RTL Architect at Synopsys with over 18 years of expertise in FPGA design, emulation, and validation across various domains, including high-speed interfaces and storage solutions. They hold 10 US patents and have authored numerous technical publications, showcasing a commitment to innovation. Tejinder’s past roles include engineering positions at STMicroelectronics and Xilinx, where they led teams and developed advanced platforms for high-speed protocols such as MIPI and NVMe. They earned a B.Tech in Electrical, Electronics, and Communications Engineering from Shaheed Bhagat Singh State University and a M.Tech in VLSI from Thapar Institute of Engineering & Technology.