Tushali Agarwal is currently a Senior R&D Engineer at Synopsys Inc., having previously held the position of R&D Engineer II at the same company. From 2017 to 2021, Tushali worked as a Design Engineer at both Zia Semiconductor Pvt Ltd and ST Microelectronics, focusing on memory design, bitcell characterization, and standard cell design validations. Tushali earned a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from JSS Academy of Technical Education from 2013 to 2017.
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