Uddit Agarwal is an Analog Design Engineer currently working at Synopsys Inc and has previously held similar roles at Ceremorphic, Inc. and Wipro. They completed an M.Sc. in Chemistry and a B.E. in Electrical and Electronics from the Birla Institute of Technology and Science, Pilani, in 2022. Additionally, Uddit gained experience as a Hardware Engineering Intern at Cisco Systems in 2021, where they developed a tool for parsing logs using Tcl, Python, and Perl. Uddit is actively seeking further analog design opportunities.
Location
Noida, India
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