Vansh Tyagi is currently an ASIC Verification Senior Staff Engineer at Synopsys Inc, where they have been providing expertise since 2024. Prior to this, they served as a Pre-Silicon Validation Engineer at Intel Corporation from 2021 to 2024 and held positions as a Senior RTL Design Verification Engineer at Truechip Solutions and as an RTL Design Verification Engineer at Eximius Design, among other roles. Vansh holds a Bachelor's Degree in Electronics and Communications Engineering from UPTU and a PG Diploma in VLSI Design from CDAC Pune, completed in 2016.
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