Veena Prabhu

Veena Prabhu is currently a Staff A&MS Circuit Timing Engineer at Synopsys Inc, leading a team focused on DDR IP. They previously served as an Engineering Manager at Intel Corporation, guiding a physical design team, and worked as a Senior Design Engineer at AMD, specializing in high-performance CPU cores. With extensive experience in ASIC and digital IP physical design, Veena has handled layout design and timing closure across multiple technologies, holding four US patents in physical design. They earned a Bachelor of Engineering in Electronics and Communications Engineering from R.V. College of Engineering in 2007.