Veera K. has a robust background in memory and AMS characterization, having served as an AMS cell characterization engineer at Wipro from 2016 to 2019 and then as a memory characterization engineer at Qualcomm from 2022 to 2024. Following a role at SeviTech Systems Pvt. Ltd. from 2019 to 2022, Veera took on a position as a SOC Logic Design Engineer at Intel Corporation in 2024. Currently, Veera is an Analog Design Staff Engineer at Synopsys Inc. Veera holds a Bachelor of Technology from RGUKT Nuzvid and a Bachelor of Engineering from Rajiv Gandhi University of Knowledge Technologies.
Location
Bengaluru, India
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