Vineeth TV is a Principal Engineer at Synopsys with over 13 years of experience in emulation modeling, FPGA prototyping, and RTL design and development. They hold a Master of Engineering in VLSI Design and a Bachelor of Technology in Electronics and Communications. Vineeth's career includes roles at prominent organizations such as Intel Corporation, where they worked on Palladium Z1 emulation modeling, and HCL Technologies, focusing on VLSI front-end design. Prior experiences include positions as a Project Engineer II at CDAC and Technical Lead at Aricent, where they gained expertise in DSP algorithms and RTL design.
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