Vipul Sachdeva

Vipul Sachdeva is a Principal Engineer at Synopsys, with a strong background in Functional Verification, Verilog, System Verilog, VHDL, and FPGA design. They previously held positions at nSys Design Systems and Fibcom India Ltd, focusing on ASIC and FPGA design and verification. Vipul earned a Master’s degree in ASIC Design from R. V. College of Engineering and a Bachelor’s degree in Electronics and Communication from Guru Gobind Singh Indraprastha University. Their expertise includes various aspects of verification and debugging, with a specialization in PCIe and related technologies.