Vishal Thareja, P.Eng, currently serves as the Senior Director of R&D Engineering at Synopsys Inc, a position held since October 2007, where Vishal leads initiatives to accelerate technology innovation in silicon-to-system design solutions. Prior roles at Synopsys include Senior Manager of Product Management and Senior Engineering Project Manager, overseeing the development of next-generation Memory Interface IP and serving as Product Line Owner for multiple DDR IP solutions. Vishal's technical expertise spans various roles from Test Engineer to Engineering Intern, contributing significantly to the design, testing, and verification of memory interface products. Vishal holds an M.A.Sc in Electrical and Computer Engineering and a B.A.Sc in Computer Engineering from the University of Ottawa, and is currently pursuing dual MBA degrees at Cornell Johnson Graduate School of Management and Smith School of Business at Queen's University.
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