Vishant Tyagi is a seasoned engineer specializing in mixed-signal circuit design, currently employed at Synopsys Inc since May 2024. Previously, Vishant served as a Mixed-Signal Circuit Design Engineer at Apple from August 2015 to May 2024, focusing on high-speed memory interface design. Prior experience includes roles at AMD as a MTS Design Engineer, where Vishant worked on high-speed memory interfaces and SerDes design, and at Avago Technologies as an Analog IC Design Engineer, contributing to various high-speed optical and signal processing projects. Vishant began a career as a Software Engineer at Nucleus Software, enhancing loan management applications. Educational qualifications include a Master of Science in Electrical Engineering from the University of Southern California and a Bachelor of Technology in Electronics & Communication Engineering from Jaypee Institute of Information Technology.
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