Vistrita Tyagi has a strong educational background with a Bachelor of Technology in Electronics and Communication Engineering from Krishna Engineering College, Ghaziabad, and a Master of Technology in VLSI Design from Banasthali Vidyapith. Vistrita began professional experience as a Student Intern at CSIR-CEERI from July 2017 to April 2018 and subsequently worked as a Senior Project Fellow. Since December 2018, Vistrita has been employed at Synopsys Inc as a DFT R&D Engineer, contributing expertise in design for testability within the semiconductor industry.
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