Vivek Pandey is a Design Automation Engineer with over 6 years of experience in CAD development and semiconductor design automation, currently serving as a Staff R&D Engineer at Synopsys Inc. They previously worked at Intel Corporation as an EDA Tools Hardware Engineer and developed expertise in scripting and automation during their tenure at Synopsys as both a Graduate Engineer Trainee and an R&D Engineer. Vivek holds a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Dr. A.P.J. Abdul Kalam Technical University and has completed additional training in Verilog and FPGA. Passionate about creating efficient workflows, Vivek thrives in solving complex challenges in the semiconductor industry.
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