Vivek Patel is a Manager at Synopsys, having transitioned through various engineering roles since 2013. They were previously an R&D Engineer and R&D Senior at Synopsys, following a stint as a Consultant Design Engineer at ARM Embedded Technologies and a Design Engineer at Si2chip Technologies. Vivek began their career as an Analog Validation Engineer at Intel, where they focused on improving the analog verification flow for advanced technologies. They hold a Master's degree in VLSI Design from Nirma Institute and a Bachelor's degree in Electronics & Communication from CK Pithawalla.
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