Vivek Tyagi is an Analog Design Engineer currently serving as a Senior Staff Engineer at Synopsys Inc since 2025. Previously, Vivek held positions as a Lead Design Engineer at Cadence Design Systems and as a Senior Design Engineer at both Micron Technology and STMicroelectronics. Earlier in their career, Vivek contributed as a Teaching Assistant at IIIT-Delhi and completed a Bachelor of Technology in Electrical, Electronics and Communications Engineering at IMS Engineering College Ghaziabad, followed by a Master of Technology in VLSI at Indraprastha Institute of Information Technology, Delhi.
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