Vyshnavi Bysani is a results-driven Senior Physical Design Engineer with over six years of experience in DDR PHY projects, specializing in technology nodes of 5nm, 7nm, 12nm, and 16nm. Having held full ownership of blocks from RTL to GDS, they successfully contributed to complex designs and implemented automated scripts for efficiency. Vyshnavi previously worked at Ambit Semiconductors and Insemi Technology Services, and is currently a Staff Engineer in ASIC Physical Design at Synopsys Inc. They hold a Bachelor's degree in Electronics and Communications Engineering from SCSVMV University, which they completed in 2017.
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