Wenxin Wang

Wenxin Wang is a Senior Staff R&D Engineer at Synopsys Inc, where they have worked since 2018 on various projects related to FPGA products, including PCIe, USB, and UFS protocols. They contributed to the design and maintenance of an emulation system and were part of a team that developed a patented trace buffer protocol. Previously, Wenxin held roles as a Design Engineer at Sigma Designs and as an intern at China Unicom. Wenxin earned a Bachelor's degree in Telecommunications Engineering from both Queen Mary University of London and Beijing University of Post and Telecommunications, followed by a Master's degree in Electrical and Electronics Engineering from the University of Southern California.