Xin Ouyang is a Senior Application Engineer at Synopsys Inc, specializing in stdcell characterization flow and providing expert support for Electronic Design Automation tools. They have extensive experience in library characterization, VLSI design, and analog integrated circuit design, utilizing tools such as Cadence Virtuoso and Synopsys Siliconsmart. Xin previously worked at Cisco Systems as a Hardware Engineer and served as a Research Assistant at the University of Pennsylvania, where they designed and tested various VLSI circuits. Xin holds a Master of Engineering in Electrical Engineering from the University of Pennsylvania and a Bachelor's degree in Power System and Automation from North China Electric Power University.
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