Xiyue Wang

Xiyue Wang is a skilled Staff ASIC designer at Synopsys Inc, specializing in firmware development since November 2022. Xiyue's expertise includes enabling Nightly Data Sanity Testing on the Jenkins platform and developing critical firmware features for switching between reference clock frequencies in advanced systems. Previous experience includes a role as a Senior Engineer at Peraso Inc., where firmware development encompassed PHY frequency switching and VCO Gain Calibration routines. Additionally, Xiyue worked as a Senior Device Software Engineer at Peraso Inc., a Silicon Validation intern at Apple, and held various positions at Pleora Technologies focusing on hardware engineering and verification. Xiyue holds a Bachelor of Engineering in Computer Engineering from the University of Waterloo.