Yash Dhillon

Yash Dhillon is a Staff ASIC Design Engineer currently working on the digital design of the PHY layer for high-speed interface IP (SerDes) at Synopsys, focusing on multiple protocols, including Ethernet and PCIe. Yash's expertise involves developing algorithms from system-level modeling to RTL implementation, emphasizing power-performance-area optimization. Previously, Yash interned at American Express and Progression, enhancing their skills in sales, marketing, and network infrastructure management. Yash holds a Bachelor of Technology in Electrical, Electronic, and Communications Engineering from Bharati Vidyapeeth's College of Engineering and a Master of Engineering in Electrical and Computer Engineering from the University of Toronto.