Yash Pathak is a Senior Validation Engineer at Synopsys Inc, a position held since 2025. Prior to this role, Yash served as a Physical Design Engineer at AndGate Informatics Pvt. Ltd. from 2024 to 2025. Yash hold's a Master of Technology in VLSI Design from the National Institute of Technology Delhi, completed in 2024, and a Bachelor of Technology in Electronics and Communication Engineering from Veer Bahadur Singh Purvanchal University, Jaunpur, earned in 2022.
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