Yingli Ren

Yingli Ren is a seasoned engineering professional with extensive experience in the semiconductor industry. Currently serving as a Senior Staff Engineer at Synopsys Inc since September 2010, Yingli focuses on silicon debugging and memory test vector generation. Previously held roles include Senior Manager of R&D at a major semiconductor company, where five 22nm and 14nm finFET memory test chips were successfully taped out under stringent industry standards. Before that, Yingli was Director of Test Chip Design & Integration Methodology at Virage Logic, developing ASIC design flows and IP validation techniques. Early career experiences include roles at Lattice Semiconductor, Altera, Fujitsu Microelectronics, and Integrated CMOS Systems, contributing to foundational EDA tool support and ASIC design processes. Yingli holds a Master's degree in Microelectronics from Santa Clara University and a Bachelor's degree in Electrical Engineering from Stanford University.