Yogesh Kumar is a Staff Engineer in Analog Design at Synopsys, currently contributing to the IO Design Team. They have experience designing biasgen blocks for eMMC PHY and GPIO, and have worked with various technologies including GF 40nm, 28nm, TSMC 12nm, and 6nm. Yogesh also previously served as a Senior Analog Design Engineer at Synopsys and as a Trainee A&MS Circuit Design Engineer at MosChip. They hold an M.Tech from Dr. B R Ambedkar National Institute of Technology, Jalandhar, where they also served as Corporate Relations Manager. Additionally, Yogesh is a fitness enthusiast, known for being focused, calm, and passionate.
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